1. Technical Field
The present invention is in the field of non-volatile programmable integrated circuits using standard CMOS technology.
2. Related Art
FIG. 1 is a circuit diagram of a conventional differential floating gate non-volatile memory circuit 100, which includes p-channel (PMOS) field effect transistors 101-105 and differential sense amplifier 106. Non-volatile memory circuit 100 uses a differential configuration, wherein a data bit is represented by the charge stored on the two floating nodes FG0 and FG1. Non-volatile memory circuit 100 is described in more detail in U.S. Pat. No. 6,950,342. Non-volatile memory circuit 100 is a complex circuit that requires a large per-bit layout area. Moreover, non-volatile memory circuit 100 requires at least 4-5 current branches to enable program, erase and read operations. Finally, non-volatile memory circuit 100 does not provide for a margin read operation to test the reliability of the circuit. Consequently, memory circuit 100 will exhibit low reliability/quality.
FIG. 2 is a cross sectional view of a conventional electrically-alterable non-volatile memory cell 200, which includes a coupling capacitor 202, a read transistor 204, and a tunneling capacitor 206. The coupling capacitor 202 includes a first gate 208, a first P+ doped region 210, a first N+ doped region 218, a first spacer 230, a second spacer 232, an insulating material 228, an N+ doped well region 234, N+ contacts 245 and P+ contacts 246. Coupling capacitor 202 is isolated by trench isolations 236 and 238. The tunneling capacitor 206 includes a second gate 226, a second N+ doped region 224, a second P+ doped region 222, a third spacer 246, a fourth spacer 248, insulating material 228, N+ doped well region 234, N+ contacts 250 and P+ contacts 251. Tunneling capacitor 206 is isolated by shallow trench isolations 240 and 242. The read transistor 204 includes a third gate 220, a third N+ region 252, a fourth N+ region 254, a fifth spacer 256, a sixth spacer 260, insulating material 228, P-substrate 244, a drain terminal 262 and a source terminal 264. Non-volatile memory cell 200 is described in more detail in U.S. Pat. No. 6,788,574 (the '574 patent).
The fabrication of non-volatile memory cell 200 requires the formation of gates 208 and 226, which are each composed of both N+ doped material 259 and P+ doped material 258. Formation of the P+ doped regions 258 of gates 208 and 226 requires a process more complicated than a standard CMOS process. In addition, the '574 patent does not provide for a margin read operation to test the reliability of non-volatile memory cell 200. (Indeed, the '574 patent does not provide details of the read circuitry used to access non-volatile memory cell 200.) Consequently, non-volatile memory cell 200 will exhibit low reliability/quality.
FIG. 3 is a circuit diagram of a conventional non-volatile memory element 300, includes access transistor 302, writing capacitor 304 and anti-fuse element 306. Non-volatile memory element is programmed by shorting the gate oxide of anti-fuse element 306. Non-volatile memory element 300 implements destructive (one-time only) programming, which severely limits the use of this element. Moreover, shorting the gate oxide typically requires significant current and power consumption. Non-volatile memory element 300 is described in more detail in U.S. Pat. No. 6,775,197.
It would therefore be desirable to have a non-volatile memory cell that overcomes the above-described deficiencies of conventional non-volatile memory systems. More specifically, it would be desirable to have a non-volatile memory system that can be fabricated using a conventional CMOS process, does not require excessive layout area, provides for a margin read operation, is reprogrammable, and minimizes power consumption.